1. Field of the Invention
The present invention relates to a method for forming a metal interconnection layer of a semiconductor device, and more particular to, a method for forming a metal interconnection layer of a semiconductor device having a via contact of a single damascene structure by using a modified dual damascene process.
2. Description of the Related Art
As semiconductor device integration increases, distances between metal interconnection layers decrease, resulting in a need for a metal interconnection layer having a multi-layered interconnection structure. Multi-layered interconnection structures are affected by the problems of parasitic capacitance (C) and parasitic resistance (R) between adjacent metal interconnection layers in the same layer or between vertically adjacent interconnection layers.
Parasitic capacitance (C) and parasitic resistance (R) in the metal interconnection system induce parasitic RC delay, and therefore, reduce the operational speed of the semiconductor device. Further, parasitic capacitance (C) and parasitic resistance (R) increase the amount of current leakage and the overall power consumption of a chip. Therefore, it is important that a multi-layered interconnection technology have a low parasitic RC when implemented in a high-speed and high-integrated semiconductor device.
To form an interconnection having a low parasitic RC, a metal having a low resistivity is needed as an interconnection material, or a dielectric film is needed with a material of a low dielectric constant. For example, materials such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), including their alloys, and the like, are possible interconnection materials.
Among these materials, copper benefits from low price and low process load as well as low resistivity. Moreover, in contrast to aluminum, copper has a greater tolerance against electro-migration.
The advantages of copper have resulted in copper being widely used as an interconnection material. However, when an interconnection of a final interconnection layer is formed of copper, an aluminum bounding pad is needed. If the interconnection of the final interconnection layer is formed of aluminum, the additional formation of the aluminum bonding pad is not needed.
However, via contacts connecting an interconnection of the final interconnection layer and an electric conductor formed in a lower layer of the final interconnection layer are typically made of copper. That is, single damascene structures, which are typically used for via contacts, are made of copper.
Single damascene structure via contacts formed by using copper are also widely used in structures connecting upper conductors and lower conductors. In addition, as the number of interconnection layers increases with the degree of integration, the number of contacts connecting upper interconnections and lower interconnections, and the depth of the contacts, increases.
Copper has a chemical affinity with other materials, and thus easily spreads into a silicon substrate or a silicon oxide film. To prevent copper from spreading and to improve an adhesive force, a method of forming a barrier layer, made of metal alloys comprising titanium or a tantalum series, between the contact and the silicon oxide film is typically used.
Further, copper has a high degree of oxidation and is easily oxidized when exposed to air. Oxidation of copper increases an interconnection resistance and stress, and negatively affects electronic characteristics of the chip. Therefore, an oxidation prevention film is formed on the outside of copper interconnection layer so as to prevent the oxidation of the copper.
In addition, a damascene process can be used for forming an interconnection pattern of copper rather than an etch. This is because copper is difficult to etch. The damascene process can be a single damascene process or a dual damascene process. In the damascene process, a planarization process is needed to remove a copper film. For a via contact formed using copper, recesses occurring in the via contact are a problem caused by different etching rates of the via contact metal and surrounding materials during the planarization process.
FIG. 1 is a graph showing recess depths in the via contact after a chemical mechanical polishing (hereinafter referred to as “CMP”) according to a distance to an adjacent via pattern.
As shown in the graph, if copper is deposited and then the CMP process is performed, a recess occurs to a certain depth in the via contact. Further, the more isolated a via contact is from an adjacent pattern, the deeper the recess is formed in comparison to a recess formed in a via contact that is close to an adjacent pattern.
As described above, if a recess occurs in the via contact, resistance increases, and the characteristics of the device are degraded. Also, where a recess is sufficiently deep in the via contact, for example, where the via contact is isolated from an adjacent pattern, an upper interconnection may be disconnected from a lower interconnection. In this case, faulty interconnections may occur.
Therefore, a need exists for a method for forming a metal interconnection layer of a semiconductor device that substantially prevents a recess from forming in a via contact.